1. Field of the invention
The present invention relates to a signal processing device, and more specifically to a signal processing device for converting into a digital signal a signal charge amount outputted from an electric charge transfer device typified particularly by a charge transfer device type image sensor and a charge transfer device type delay line.
2. Description of Related Art
In the prior art, in the case of processing in the form of a digital signal an analog signal outputted from a charge transfer device type image sensor or a charge transfer device type delay line, for example, as shown in FIG. 1, an analog signal outputted from a charge transfer device type image sensor 61 is caused to pass through a buffer 66, a clamp circuit 67, a sample-hold circuit 68, a low pass filter 69, and an amplifier 70 for various signal processings, and thereafter, the analog signal is supplied an A/D converter (analog-to-digital converter) 71, so that a digital signal is obtained. This method has required a number of circuit elements, and the circuit designing and the signal processings for this method must use a complicated analog signal processing technique, which has become a hindrance in making the circuit designing easier.
For reference, as extremely simply depicted in FIG. 1, the charge transfer device type image sensor 61 is basically composed of a number of photosensor cells such as photodiodes 62 arranged in the form of a matrix having a plurality of rows and a plurality of columns, a plurality of vertical charge transfer devices each located along a corresponding column of photodiodes so as to receive an electric charge from all the photodiodes of the corresponding column in parallel and to vertically transfer the received electric charges, a horizontal charge transfer device located along an output end of all the vertical charge transfer devices so as to receive an electric charge from all the vertical charge transfer devices in parallel and to horizontally transfer the received electric charge, and an electric charge detection circuit 65 having an input coupled to an output end of the horizontal charge transfer device. An output of the electric charge detection circuit 65 is connected to the buffer 66.
Japanese Patent Application Laid-open Publication No. JP-A-61-184978 has proposed a signal processing device which attempts to improve the above mentioned problems and includes a charge coupled device (abbreviated "CCD" hereinafter) as the charge transfer device
The proposed signal processing device includes two two-bit A/D converters so that one of the two-bit A/D converters is used for the more significant two bits, and the other two-bit A/D converter is used for the least significant two bits, whereby a resolution of 4 bits per sample can be obtained in total.
Referring to FIG. 2, there is shown a block diagram illustrating the construction of the A/D converter disclosed in the above referred Japanese patent application laid-open publication. FIGS. 3A and 3B are tables illustrating an operation of the shown A/D converter.
The shown A/D converter includes a tapped CCD delay line 31, which is coupled to an output of a CCD image sensor or delay line so as to receive a signal electric charge transferred in a transfer direction 32. The signal electric charge is transferred through the tapped CCD delay line 31. Simultaneously, at each time the signal electric charge is transferred one stage within the tapped CCD delay line 31, the magnitude of the signal electric charge is nondestructively detected, so that a signal voltage is applied from signal electric charge output terminals 33, 34 and 35 to a signal input terminal of analog comparators 39, 38 and 37 included in an analog comparator group 36. Assuming that a reference voltage is V.sub.R, a reference voltage terminal of these analog comparators 37, 38 and 39 are supplied with 3V.sub.R /4, V.sub.R /2, and V.sub.R /4, respectively, which are generated in a reference voltage generation circuit 40.
Here, operation of the analog comparator 37 will be explained. If a signal voltage V.sub.S detected in the tapped CCD delay line 31 is larger than 3V.sub.R /4 (V.sub.S &gt;3V.sub.R /4), the analog comparator 37 brings its output discrimination signal C.sub.1 into a high level "1". If the relation of V.sub.S &lt;3V.sub.R /4 holds, the discrimination signal C.sub.1 is brought into a low level "0". The other analog comparators 38 and 39 operate similarly, except that the applied reference voltage is V.sub.R /2 or V.sub.R /4.
Accordingly, in the case of V.sub.S &gt;3V.sub.R /4, all discrimination signals C.sub.1, C.sub.2 and C.sub.3 outputted from the analog comparators 37, 38 and 39, respectively, become the high level "1". In the case of 3V.sub.R /4&gt;V.sub.S &gt;V.sub.R /2, the discrimination signals C.sub.2 and C.sub.3 become the high level "1". In the case of V.sub.R /2&gt;V.sub.S &gt;V.sub.R /4, only the discrimination signal C.sub.3 becomes the high level "1". In the case of V.sub.R /4&gt;V.sub.S, all of the discrimination signals C.sub.1, C.sub.2 and C.sub.3 become the low level "0".
The discrimination signals C.sub.1, C.sub.2 and C.sub.3 outputted from the analog comparators 37, 38 and 39, are respectively supplied to digital shift registers 41, 42 and 43 having different delay times for compensating the fact that the detection for the same signal charge is delayed one clock by one clock from the terminal 33 to the terminal 34 and also from the terminal 34 to the terminal 35, as would be apparent from the operation of the tapped charge transfer device delay line 31. For this purpose, the digital shift registers 41, 42 and 43 are driven by a clock having the same frequency as that of a clock for driving the tapped charge transfer device delay line 31, and the delay times of the digital shift registers 41, 42 and 43 are selected to correspond to the delay time occurring in the tapped charge transfer device delay line 31.
The discrimination signals C.sub.1, C.sub.2 and C.sub.3 thus adjusted to have concurrency by action of the digital shift registers 41, 42 and 43, are supplied to an encoder 44, where the discrimination signals C.sub.1, C.sub.2 and C.sub.3 are converted to binary signals D.sub.1 and D.sub.2 of two bits as shown in FIG. 3A. Thus, with the above mentioned operation, the A/D conversion for obtaining two most significant bits can be realized.
Furthermore, the discrimination signals C.sub.1, C.sub.2 and C.sub.3 are applied to a bias electric charge generator 45, which is configured to generate and add a bias electric charge corresponding to V.sub.R /4 for each of the discrimination signals C.sub.1, C.sub.2 and C.sub.3 when the discrimination signal is at the low level "0". Namely, as shown in FIG. 3B, when all of the discrimination signals C.sub.1, C.sub.2 and C.sub.3 are at the high level "1", no bias electric charge is generated and added. When only the discrimination signal C.sub.1 is at the low level "0", a bias electric charge corresponding to V.sub.R /4 is generated, and added to the electric charge outputted from the tapped charge transfer device delay line 31, in a bias electric charge adder 46. If both of the discrimination signals C.sub.1 and C.sub.2 are at the low level "0", a bias electric charge corresponding to V.sub.R /2 is generated and added in the bias electric charge adder 46. In the case that all of the discrimination signals C.sub.1, C.sub.2 and C.sub.3 are at the low level "0", a bias electric charge corresponding to 3V.sub.R /4 is generated and added in the bias electric charge adder 46.
The signal electric thus added with the bias electric charge is supplied from the bias electric charge adder 46 to another tapped charge transfer device delay line 47 so as to be transferred through the tapped charge transfer device delay line 47. Similarly to the tapped charge transfer device delay line 31, the electric charge through the tapped charge transfer device delay line 47 is nondestructively detected at each one of the stage transfer operation, so that a synthetic signal voltage is applied from signal electric charge output terminals 48, 49 and 50 to a signal input terminal of analog comparators 54, 53 and 52 included in another analog comparator group 51. On the other hand, a reference voltage terminal of these analog comparators 52, 53 and 54 are supplied with 15V.sub.R /16, 14V.sub.R /16, and 13V.sub.R /16, respectively, which are generated in a reference voltage generation circuit 55.
Here, assuming that the synthetic signal voltage outputted from signal electric charge output terminals 48, 49 and 50 is expressed by V.sub.C, in the case of V.sub.C &gt;15V.sub.R /16, all discrimination signals C.sub.4, C.sub.5 and C.sub.6 outputted front the analog comparators 52, 53 and 54, respectively, become the high level "1". In the case of 15V.sub.R /16&gt;V.sub.S &gt;14V.sub.R /16, the discrimination signals C.sub.5 and C.sub.6 become the high level "1". In the case of 14V.sub.R /16&gt;V.sub.S &gt;13V.sub.R /16, only the discrimination signal C.sub.6 becomes the high level "1" In the case of 13V.sub.R /16&gt;V.sub.S (&gt;12V.sub.R /16), all of the discrimination signals C.sub.4, C.sub.5 and C.sub.6 become the low level "0".
Here, since the bias electric charge component included in the synthetic signal voltage V.sub.C is "0", V.sub.R /4, V.sub.R /2 or 3V.sub.R /4, the discriminating condition for the signal voltage V.sub.s can be sorted into 16 kinds as shown in FIG. 3B.
The discrimination signals C.sub.4, C.sub.5 and C.sub.6 outputted from the analog comparators 52, 53 and 54, are respectively supplied to digital shift registers 56, 57 and 57 having different delay times for compensating differences in the delay time. The discrimination signals C.sub.4, C.sub.5 and C.sub.6 thus adjusted to have concurrency by action of the digital shift registers 56, 57 and 57, are supplied to an encoder 59, in which the discrimination signals C.sub.4, C.sub.5 and C.sub.6 are converted to binary signals D.sub.3 and D.sub.4 of two bits as shown in FIG. 3B. Thus, an A/D conversion section for obtaining two least significant bits can be constituted of the tapped charge transfer device delay line 47, the analog comparator group 51, the reference voltage generation circuit 55, the digital shift registers 56, 57 and 58, the encoder 59.
Accordingly, with combination of the two least significant bits D.sub.3 and D.sub.4 with the two most significant bits D.sub.1 and D.sub.2, an A/D converter having a resolution of 4 bits per sample can be acheived.
However, the above mentioned signal processing device for converting the analog signal to the digital signal had to include a number of nondestructive electric charge detection circuits and reference voltages in correspondence to the number of the electric charge amounts to be detected. In addition, for constituting the four-bit A/D converter, there are required six analog comparators, six digital shift registers, and six charge transfer delay line stages. Furthermore, since the digital output signals are synchronized to have concurrency in time by the digital shift registers, the circuit construction inevitably becomes complicated.